1. Field
Exemplary embodiments of the present invention relate to a variable resistance memory device and a method for operating the same, and more particularly, to a variable resistance memory device having a cross point cell array configuration and a method for operating the same.
2. Description of the Related Art
A variable resistance memory device (or a resistance variable memory device) changes its resistance value between at least two resistance states depending on an external input. The variable resistance memory device stores data using such a resistance changing property and includes a Resistive Random Access Memory (ReRAM) device, a Phase Change RAM (PCRAM) device, a Spin Transfer Torque-RAM (STT-RAM) device, etc. Many studies have been done on various variable resistance memory devices since they have a simple structure and good non-volatile properties.
Among them, a ReRAM device may include upper and lower electrodes and a variable resistance layer that is disposed between the upper and lower electrodes and formed of, for example, a Perovskite-based material or transitional metal oxide. In the ReRAM device, a filament as a current path is created in or removed from the variable resistance layer depending on a level of a voltage applied to the upper and lower electrodes.
When the filament is created, the variable resistance layer is at a low resistance state. In contrast, when no filament is present, the variable resistance layer is at a high resistance state. Switching from the high resistance state to the low resistance state is called a ‘set’ operation, and switching from the low resistance state to the high resistance state is called a ‘reset’ operation.
FIGS. 1A to 1C are plane views illustrating a conventional variable resistance memory device.
Referring to FIG. 1A, the variable resistance memory device has a cross point cell array configuration where memory cells MCs are arranged at cross points where a plurality of bit lines BL0˜BL7 extending in parallel to each other intersects with a plurality of word lines WL0˜WL7 extending in parallel to each other.
Data stored in a given memory cell, e.g., the selected memory cell SMC of FIG. 1A, is read out by applying a ground voltage GND to a selected word line, e.g., WL3, applying a given voltage V to a selected bit line, e.g., BL0, and detecting a current flowing through memory cell SMC. The current flowing through memory cell SMC varies depending on a resistance state of memory cell SMC.
In the cross point cell array configuration, a voltage having a certain level, which is less than that of the given voltage V applied to the selected memory cell SMC, may be applied to unselected memory cells. As a result, a current may leak through the unselected memory cells as indicated by dotted arrow lines in FIG. 1A.
Referring to FIG. 1B, the variable resistance memory cell device includes a plurality of memory cell arrays MCA0˜MCA3, each including memory cells arranged in a matrix pattern. In a peripheral region of each of the memory cell arrays MCA0˜MCA3, a plurality of core circuits CC necessary for an operation of the variable resistance memory device may be provided.
As a size of each of the memory cell arrays MCA0˜MCA3 increases, the leakage current increases as well, degrading reliability of the variable resistance memory device. In addition, the greater the memory cell array size, the greater an area occupied by the core circuits. Thus, the increase of the memory cell array size may be limited. As a result, it is difficult to increase a degree of integration of the memory device.
Referring to FIG. 1C, a hierarchical bit line structure, which includes global bit lines GBL0˜GBL2 and a plurality of local bit lines BL0˜BL5, was suggested to suppress the leakage current generated in the cross point cell array configuration. (see A. Kawahara et al., “An 8 Mb Multi-Layered Cross-Point ReRAM Macro with 443 MB/s Write Throughput,” in Proc. of ISSCC, 2012)
However, in the hierarchical bit line structure shown in FIG. 1C, additional transistors such as transistor TR are required for selecting the local bit lines BL0˜BL5 and a plurality of selection lines SL0˜SL3 to couple the local bit lines BL0˜BL5 to the global bit lines GBL0˜GBL2. In addition, the memory cell arrays formed using multiple layers occupy a large area, and thus a degree of memory cell integration may decrease.